Communication Synthesis for Recon gurable Embedded Systems

In this paper we present a methodology and a design tool for communication synthesis in recon gurable embedded systems Using our design tool the designer can focus on the functional behavior of the design and on the evaluation of di erent mappings All the low level details of the recon gurable resource e g a multi FPGA architecture are hidden After the application s tasks have been bound to FPGAs and a multi con guration schedule has been generated the communi cation synthesis step provides the necessary interfaces between tasks Interface circuitry is automatically inserted to connect communicating tasks whether they are mapped onto the same or onto di erent FPGAs This includes multiplexing several logical communication channels over one physical channel inserting routing tasks and providing dedicated interfaces that solve the problem of intercon guration communication Introduction During the last years recon gurable computing has gained interest not only as a potentially new paradigm for general purpose computing but also for em bedded systems Recon gurable systems are often classi ed according to their recon guration model into compile time recon guration CTR and run time recon guration RTR In CTR hardware compilation and recon guration i e downloading the design onto a recon gurable device are done at compile time In embedded systems this recon guration model is mainly used for rapid prototyping However recon gurable hardware can be a viable alternative to ASICs for the nal system implementation when the expected volume is rather low and performance constraints are met In RTR the con guration of the re con gurable device is changed while the application is running There are two application scenarios for RTR in embedded systems The rst scenario are em bedded systems where frequent hardware updates are expected e g network switches that may be recon gured to support di erent topologies Usually these systems operate in a time critical execution mode and a not time critical update mode The second scenario are embedded applications that are split into time exclusive parts A recon gurable resource is used to execute these parts se quentially By this cost can be signi cantly reduced compared to an all in ASIC or an all in FPGA solution To develop system design tools for embedded recon gurable systems some of the synthesis tasks have to be revisited scheduling binding and communica tion synthesis For RTR systems the scheduling binding step must respect that communicating hardware tasks can be grouped into several con gurations that are executed sequentially on the same resource A recon guration schedule has to be found and a controller that initiates and controls recon guration has to be synthesized This problem has already received some attention The second major issue is communication synthesis Communication synthesis has been attacked in several projects However for embedded recon gurable systems the automatic generation of communication and interface circuitry leads to new problems and is of utmost importance for the following reasons First the manual interface construction formulti FPGA systems is extremely tedious The designer is considered with all the low level details including the number and positions of available I O pins I O pins reserved for system signals and I O pins connecting to other FPGAs and memories If communicating tasks are mapped onto di erent FPGAs the available number of wires connecting the FPGAs may be insu cient to implement all the required communication channels In this case some form of multiplexing logical channels over physi cal wires must be used Communicating tasks mapped onto FPGAs that are not directly connected require the insertion of routing nodes Second a problem unique to RTR systems is intercon guration communication If two commu nicating tasks are executed sequentially a means of transferring the data from the sender task to the receiver task must be provided Given a partially recon g urable FPGA device such as the Xilinx XC xx part of the FPGA area can be reserved to implement a communication bu er In the case that the resources can only be recon gured globally data has to be stored temporarily in an external memory In this paper we present CORES HASIS a communication synthesis tool set for embedded recon gurable systems Using this tool the designer can focus on the functional behavior of the design and on the evaluation of di erent map pings Interface circuitry is automatically inserted to connect communicating tasks whether they are mapped onto the same or onto di erent FPGAs This includes multiplexing routing and dedicated interfaces that solve the problem of intercon guration communication by temporarily bu ering data in the system s memories Synthesis of Recon gurable Systems Generally system synthesis starts from a speci cation model and re nes this model iteratively until the implementation model is reached The three tasks that usually comprise system synthesis are allocation binding and scheduling The speci cation model consists of three parts a problem graph an architec ture graph and implementation constraints The problem graph represents the functional objects of the application In our methodology the problem graph is a directed acyclic graph with two kinds of nodes tasks and queues Tasks are functional objects with an associated executable code circuit that is stored in an implementation library Tasks read data from and write data to ports The ports are characterized by their bit width and use handshake signals to implement an asynchronous communication protocol On termination a task raises its done ag Queues are bu ers with FIFO semantics that connect two tasks Directly connected tasks denote unbu ered communication queues allow for bu ering A queue has a size width depth and an access mode blocking non blocking Edges in the problem graph denote data ow The architecture graph has three kind of nodes FPGAs memories and buses The edges of the architecture nodes indicate the connections between FPGAs memories and buses An allocation FPGA memory bus task p queue p p routing node p interface node p data ow edge p p p Table Possible bindings is a subset of the architecture graph i e a set of FPGAs memories and buses that is su cient to implement the problem graph A binding maps each object of the problem graph tasks queues onto some resource of the architecture graph The possible bindings are shown in Table A binding induces also a mapping of data ow edges to paths in the architecture graph A schedule assigns a starting time to each task In pure CTR systems there exists only one con guration for each FPGA All the speci ed tasks and queues are loaded con gured onto the FPGA before the application starts Tasks are active from beginning and can be blocked by a read from a channel if the required data is not yet available In RTR systems each FPGA may undergo a sequence of con gurations A new con guration can be loaded if all the tasks in the current con guration have completed The individual done ags from the tasks are combined to form the con guration s done ag All the con gurations done ags are collected by the recon guration controller This function usually located at the host executes the static recon guration schedule Communication synthesis is a synthesis step that is applied after al location binding and scheduling Our communication synthesis tool suite CORES HASIS expects as input a re ned speci cation graph i e allocation binding and scheduling have already been done by either a system synthesis tool or manually by the designer The CORES HASIS tool suite splits the re ned problem graph into several smaller problem graphs one for each resource and con guration Then interface nodes and routing nodes are inserted Inter faces nodes establish FPGA to FPGA and FPGA to memory communication and multiplex several logical channels over a limited number of physically avail able wires Routing nodes are required when two communicating objects are mapped onto non adjacent FPGAs Interface and routing nodes are bound to FPGAs as shown in Table Communication Synthesis Communication synthesis for recon gurable systems deals with the connection of tasks and queues bound to arbitrary FPGAs and memories in one or several con gurations Fig presents a taxonomy of the di erent communication types for the basic task queue task system In CTR systems there is only on o chip communication On chip communication is the simplest communication type and occurs between tasks or tasks and queues O chip communication involves two FPGAs or an FPGA and a memory This communication type can induce routing and multiplexing In RTR systems intercon guration communication is required partially reconfigurable FPGAs only valid for 7 on FPGA queue in memory configuration configuration off-chip configuration off-chip